Conferences/Workshops/continuing-education-programmes Organized
Coordinator (With Dr. A. S. Mandal, CEERI Pilani & Mr. D. Boolchandani)
IEP on Memory Design & Testing, MNIT Jaipur, (in cooperation with IIT Delhi, and CEERI Pilani), Dec. 2010
Coordinator
Tutorial cum Workshop on Advances in VLSI Design, 9th Aug. 2010, MNIT Jaipur
Co-coordinator
IEP on System modeling using VHDL/SystemC/System-Verilog, Thapar Institute of Engg. & Technology, organized by CEERI, Pilani & Thapar Institute, Patiala alongwith MNIT Jaipur (SMDP-VLSI-2 project of Ministry of Comm. & IT), 14th - 21st December 2009.
Fellowship Chair
22nd IEEE International Conference on VLSI Design, 5-9 January 2009, New Delhi
Convener,
Institution of Engineers’ All India Seminar on Advance Electronic Systems: Modeling and Simulation (Verification), 9-10 Aug. 2008, Jaipur
Co-convener
TEQIP & CEP Workshop on Curriculum Structure Development, December 3, 2007 MNIT Jaipur
Member, organizing committee
Seminar on Research & higher Studies: Collaboration with EPFL, Switzerland, 27th Sept. 2007, MNIT Jaipur.
Coordinator
TEQIP & CEP Workshop on Learning Theory & Support Vector Machines, May 28, 2007, MNIT Jaipur
Member, organizing committee
TEQIP Workshop on Learning Intellectual Property Rights, May 26-27, 2007, MNIT Jaipur
Principal Coordinator
AICTE Faculty Development programme on “Challenges in System-on-Chip Design & Verification”, Dec. 19-28, 2006, MNIT, Jaipur
Member, Organizing committee & technical programme committee
Institute of Engineers (I) National Convention & Seminar on Advances in Electronics and
Telecommunication: Vision 2020, Jaipur, 4-5 August 2006.
Organizing committee member
National Symposium on Broadband communication, Jaipur April 8-9, 2006.
Organizing committee member
National Symposium on Mobile handsets, Jaipur April 10-11, 2005.
Principal Chair
VLSI Education Workshop 2005, March 8-12, 2005
Principal Coordinator
ISTE/AICTE STTP on “Reconfigurable computing using FPGAs”, Feb 25-29, 2004 MNIT, Jaipur
Principal Coordinator
ISTE/AICTE Short Term Training Programme (STTP) on “Designing CMOS VLSI sub-systems”, Sept. 22-29, 2003, MNIT, Jaipur.
Principal chair
Workshop on VLSI Design for Embedded Systems, MNIT, Jaipur, Jan 4-5, 2003
Publication committee member
ISTE STTP on High Frequency Communication, Dec 9-21, 2002
Principal Coordinator
Short term Instruction Enhancement Programme on Analog ICs, MNIT, Jaipur, Sept. 7-10, 2002
Organizing committee member
IETE Annual seminar on “E-Governance”, Jaipur, May 2002.
Publication committee member
ISTE STTP on Software Quality Assurance, Dec 24, 2001-Jan 04, 2002
Publication committee member
ISTE Short term training program on VHDL and ASIC Design, Deptt. of ECE, Malaviya Regional Engg. College, Jaipur, Sept.-Oct 2001.
Organizing committee member
IETE Annual seminar on “Wireless Communications”, Jaipur, May 2001.
Finance Co-chair, Organizing committee
4th IEEE VLSI Design and Test Workshops, Delhi, Aug. 2000.
Finance co-chair, Organizing committee
3rd IEEE VLSI Design and Test Workshops, Delhi, Aug. 1999.
Finance co-chair, Organizing committee
2nd IEEE VLSI Design and Test Workshops, Delhi, Aug. 1998.
Member, Publication committee
Annual convention of Indian Society for Technical Education, Jaipur, Dec. 1996.