1. Design of IEEE compliant fast floating point adder Lava Bhargava 1999
2. Design of Analog ICs: Case of Op-Amp Anil Gehlot 1999
3. Approximate DCT algorithm for still image compression Rakesh Sharma 2002
4. Algorithms evaluation for High performance FPGA routing Manish Tiwari 2003
5. Low power arithmetic circuit design: An instance of Floating point adder G. S. Choudhary 2003
6. Simulated Annealing algorithm for low power scheduling Kanupriya Goel 2003
7. Genetic based Multi-objective Optimization Approach for FPGAs Routing Rajesh Tiwari 2004
8. On Evaluation of “March” Based Algorithms for Memory Testing Indira Rawat 2004
9. On A-Priori Interconnect prediction for FPGA Suman Morisetti 2004
10. USB based interface platform for ARM based processor system Ajay Singhal 2006
11. Digital hardware implementation of Watermarking schemes: An Evaluation L. C. Pawar 2006
12. Reduced Order modeling of non-linear systems Nidhi Agarwal 2007
13. Low power interconnect aware High level synthesis Diwakar Agarwal 2007
14. System level dynamic power management Manish Kumar 2007
15. Optimal Decap placement to minimize IR drop in Power grid Manish Verma 2008
16. Assertion based verification: A case study of select communication protocols Menaka Yadav 2008
17. System level design exploration of MPEG2 decoder Sanjay Samaria 2008
18. An approach using hybrid Kernel functions for SVM approach for generating Analog Macromodels
Abrar Ahmed 2008
19. SVM based Machine learning approach for Analog sub-systems’ feasibility classification Chandrakant Gupta 2008
20. FSM partition for low power: An evaluation of algorithms, Banasthali University 2008
21. Low power partitioning of behavioral specifications from SystemC Prafull Agarwal 2009
22. Probability based equivalence check for logic circuits Sudha Madhuri 2009
23. Low power scheduling schemes at behavioral specifications Sandeep Singh 2009
24. BIST and BISR for flash memories (dual gate structures) Renu Agarwal 2009
25. Multi-objective genetic approach for analog circuit sizing Deepak Sharma 2009
26. Process ware macromodel for rapid design centering using genetic algorithm: A case study of two-stage opamp* Jyoti Sharma 2009
27. Nano-scale devices for digital logic Pankaj Jha 2010
28. Power estimation technique for embedded systems Namita Sharma 2010
29. Exploring variability aware sizing of Analog circuits: A case study using Cascode opamp in 90nm* Lokesh Garg 2010
30. Exploring variability aware sizing of Analog circuits: A case study using VCO in 90nm Sapana Khandelwal 2010
31. Hardware implementation of low power Turbo Decoder Neha, Banasthali univ. 2010
32. Hardware implementation of low power Turbo Encoder Rasmi Bisht, Banasthali univ. 2010
33. Radiation hardening for semiconductor devices* Bharti Sharma, Banasthali Univ. 2011
34. Review & comparison of High level virtual platforms for design space exploration approaches (MPSoC) Vipin Joshi 2011
35. Power aware HW prototyping using reconfiguration: Case study of (i) SVM based Feature classifier for computer vision (ii) Color digital video interface Gauri Shankar Gupta 2011
36. Reconfiguration approaches for power aware prototyping: Case study of ATM cell assembler Alok Sharma 2011
37. Secondary effects in nanoscale devices Amit Kumar 2012
38. Variability aware Memory yield enhancement Anuj Solanki 2012
39. Memory synthesis using nanodevices Mahesh Soni 2012
40. Analog synthesis into nanometer Rajesh Sahu 2012