1. Mahanth Prasad, V. Sahula and V. K. Khanna. Design and fabrication of Si-diaphragm for ZnO-based MEMS acoustic sensor, 17th International Symposium on VLSI Design and Test, 2013, Jaipur (poster).
2. Saima Cherukat and V. Sahula. Process Variation Tolerant SRAM Design for Ultra Low Power Applications, , 17th International Symposium on VLSI Design and Test, 2013, Jaipur.
3. Nupur Navlakha, Lokesh Garg, Dharmendar, Vineet Sahula. Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals, , 17th International Symposium on VLSI Design and Test, 2013, Jaipur.
4. Mahesh Soni and V. Sahula. Power Delay Product Optimal Design of Ternary ALU using Carbon nanotubes, All India Conference on “Global Innovations in Computer Science & Engineering and Information Technology” being organized during April 12 -13, 2013 at AICON-2013, Durg.
5. R. Kumawat, V. Sahula, M. S. Gaur. Probabilistic Modeling Approaches for Nanoscale Devices, International conference on circuit, power and computing technologies ICCPCT-2013, 21-22 March 2013, Kumaracoil, TN, India.
6. R. Kumawat, V. Sahula, M. S. Gaur. Reliable circuit analysis and design using nanoscale devices, International Conference on Communication and Electronics System Design, Jaipur, Jan. 2013, Proc. of SPIE Vol. 8760 87602C-1, doi: 10.1117/12.2012516.
7. Lokesh garg and V. Sahula, Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power , International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Spain 19-21 Sept. 2012, Seville, Digital Object Identifier: 10.1109/SMACD.2012.6339387 , PAGES 253-256.
8. Mahesh Soni, R. Kumawat, V. Sahula and M. S. Gaur. Reliability Evaluation of Redundancy based Fault Tolerant Techniques at Nanoscale, Reliability Aware System Design and Test, Hyderabad, January 7-8, 2012.
9. R A Patil, G Gupta, V Sahula and A. S. Mandal. Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration, 25th IEEE International Conference on VLSI Design, (VLSID), 2012 INDIA, Digital Object Identifier: 10.1109/VLSID.2012.47 , pages 62-67.
10. Mahanth Prasad, R. P. Yadav, V. Sahula, V. K. Khanna. Design and mathematical model of a ZnO-based MEMS acoustic sensor, Proc. SPIE Proceedings on 16th International Workshop on Physics of Semiconductor Devices, Kanpur, Volume 8549, December 19-22, 2011; doi:10.1117/12.925318.
11. Mahanth Prasad, R. P. Yadav, V. Sahula, V. K. Khanna. Design and simulation of Pt-based microhotplate, and fabrication of suspended dielectric membrane by bulk micromachining, Proc. SPIE Proceedings on 16th International Workshop on Physics of Semiconductor Devices, Kanpur, Volume 8549, December 19-22, 2011; doi:10.1117/12.925318.
12. D. Mathur, S. K. Bhatnagar and V. Sahula, LTCC Technology for Wireless System in Package Architecture: Issues & Challenges, IMAPS System-level package workshop, Dec. 2011.
13. Patil, R.A.; Sahula, V.; Mandal, A.S., Facial Expression Recognition in Image Sequences Using Active Shape Model and SVM, Fifth IEEE UKSim European Symposium on Computer Modeling and Simulation (EMS), Digital Object Identifier:10.1109/EMS.2011.25, Year 2011 , Page(s): 168 – 173. (presented at CimSim, Langkawi, Malaysia, Sept. 2011).
14. Rajesh A Patil, V Sahula, AS Mandal. Automatic detection of facial feature points in image sequences, International Conference on Image Information Processing (ICIIP), 2011, Digital Object Identifier: 10.1109/ICIIP.2011.6108957 , pages 1-5.
15. R A Patil, V Sahula, A S Mandal. Bayesian versus support vector machine based approaches for facial feature classification in image sequences, IEEE International Conference on Computer and Communication 2011 India, (ICCCT), Digital Object Identifier: 10.1109/ICCCT.2011.6075168 , Pages 174-179.
16. D Mathur, S K Bhatnagar, V Sahula, Nondestructive method for measuring dielectric constant of sheet materials, TENCON 2011 IEEE Region 10 Conference, Digital Object Identifier: 10.1109/TENCON.2011.6129282 , pages 1105-1109.
17. R A Patil, V Sahula, A S Mandal. Automatic recognition of facial expressions in image sequences: A review, IEEE International Conference on Industrial and Information Systems (ICIIS), 2010, India, Digital Object Identifier: 10.1109/ICIINFS.2010.5578670 , pages 408-413.
18. D. Boolchandani, Lokesh Garg, Sapna Khandelwal and Vineet Sahula. Variability Aware Yield Optimal Sizing of Analog Circuits using SVM-Genetic Approach, XIth IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, Tunisia 4-5 Oct. 2010, Digital Object Identifier: 10.1109/SM2ACD.2010.5672332, pages 1-6.
19. U. Deshmukh, Prafull Agarwal and V. Sahula, Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture, IEEE Computer Society International Symposium on VLSI, Kefalonia, Greece, 5-7 July 2010.
20. P K Jha, V Sahula. Omnipotent and mortal training of a nanocell model to emulate the functionality of a logic gate, India Conference INDICON, 2010, Digital Object Identifier: 10.1109/INDCON.2010.5712699 , pages 1-6.
21. R. Patil, A. S. Mandal and V. Sahula, “Automatic facial expression recognition: A Review”, IEEE International Conference on Industrial and information systems (ICIIS), NITk Surathkal, July 2010.
22. R. Kumawat, V. Sahula, M. S. Gaur and V. Laxmi, Modeling and Reliability Evaluation of logic Circuits at Nanoscale, RASDAT Workshop (co-located with VLSI Design Conf.), January 7-8, 2010.
23. U. Deshmukh and V. Sahula, Stochastic Automata Network Based Approach for Performance Evaluation of bus-arbiters for System-on-Chip Communication Architectures, Region 10 Annual International conference TENCON, 23-26 Nov. 2009 Singapore, Digital Object Identifier: 10.1109/TENCON.2009.5395938, pages 1-6.
24. D. Boolchandani, Anupam Kumar and V. Sahula , Multi-objective Analog Circuit Sizing using SVM Macro-model as Evaluation function within Genetic Algorithm, Region 10 Annual International conference TENCON, 23-26 Nov. 2009 Singapore, Digital Object Identifier: 10.1109/TENCON.2009.5395927 , pages 1-6.
25. D. Boolchandani, C. Gupta and V. Sahula, Analog Circuit Feasibility Modeling using Support Vector Machine with Efficient Kernel Functions, Special Session: Design, Analysis and Tools for Integrated Circuits and Systems (DATICS'09), IAENG International Conference on Electrical Engineering (ICEE'09), IMCES, Lecture Notes in Engineering and Computer Science Year: 2009 Vol: 2175 Issue: 1 Pages/record No.: 1609-1614 Hong Kong, 18th -20th March 2009.
26. D. Boolchandani, Mohd. A. Ahmed and V. Sahula, Improved Support Vector Machine Regression for Analog Circuits using Efficient Kernel Functions, Xth IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, Germany Sept. 2008
27. U. Deshmukh and V. Sahula, SAN based approach for performance evaluation of heterogeneous SoC communication architectures, IEEE NORCHIP Conference, Tallinn ESTONIA, 17-18 Nov. 2008, Digital Object Identifier: 10.1109/NORCHP.2008.4738313, pages 208-211.
28. U. Deshmukh and V. Sahula, Analytical Approach for performance evaluation of SoC Communication architecture, IEEE International Conference on Microelectronics, Sharjah, Dec. 2008, Digital Object Identifier: 10.1109/ICM.2008.5393540 , pages 153-158.
29. Ulhas Deshmukh and V. Sahula, “Performance evaluation of Arbitration schemes of bus-based communication architectures based on Interactive Generalized Semi Markov Process Model (IGSMP)”, European Modeling & Simulation Symposium, UK, 8th -10th Sept. 2008, Digital Object Identifier: 10.1109/EMS.2008.77, pages 578-583.
30. U. Deshmukh and V. Sahula, “HCFG Approach for performance evaluation of SoC communication architecture”, 12th IEEE VLSI Design and Test Symposium, Bangalore, 23rd – 26th July 2008.
31. R. Tiwari and V. Sahula. “Cross talk Aware Multi-objective Optimal Routing for Island-Style FPGAs”, 10th IEEE VLSI Design and Test Symposium, Goa, 9-12 Aug. 2006 (full-text-pdf).
32. V. Sahula. “VLSI Curriculum in Indian Universities: An Analysis & Prescription”, 8th IEEE VLSI Design and Test Workshops, Mysore, Karnataka, Aug. 2004.
33. I. Rawat and V. Sahula. “An Evaluation of March-based Testing Algorithms Using Switch Level Model of Bit-oriented SRAM”, 8th IEEE VLSI Design and Test Workshops, Mysore, Karnataka, Aug. 2004.
34. Govind, S., Choudhury, S. and V. Sahula, Optimizing ARM7 like Processor Architecture for Video Applications (Motion Estimation), 7th IEEE VLSI Design and Test Workshops, Bangalore, Karnataka, Aug. 2003.
35. U. Chandran, D. Kuldeep and V. Sahula. Formal Verification of Finite State Machines, 6th IEEE VLSI Design and Test Workshops, Bangalore, Aug. 2002.
36. P. Jain, D. Boolchandani and V. Sahula. Power Aware Characterization of Sequence of Input-Vectors for Standard-Cell based Digital circuits, 6th IEEE VLSI Design and Test Workshops, Bangalore, Aug. 2002.
37. D. Dhawan, D. Boolchandani and V. Sahula, Layout Design of Cascode Current Mirror with Improved Current Mismatch, 6th IEEE VLSI Design and Test Workshops, Bangalore, Aug. 2002.
38. H. K. Sharma, L. Bhargava and V. Sahula. On Evaluation of Parametric Yield for an Operational Transconductance Amplifier (OTA), 6th IEEE VLSI Design and Test Workshops, Bangalore, Aug. 2002.
39. V. Sahula, C. P. Ravikumar and D. Nagchoudhuri, Improvement of ASIC design processes, IEEE 7th ASPDAC/ 15th International Conference on VLSI Design, Bangalore India, Jan. 2002, Digital Object Identifier: 10.1109/ASPDAC.2002.994893, 105-110.
40. V. Sahula and C. P. Ravikumar, Hierarchical Concurrent flow graph approach for modeling and analysis of design processes, IEEE 14th International Conference on VLSI Design, Bangalore India, Jan. 2001, Digital Object Identifier: 10.1109/ICVD.2001.902645, pages 91-96.
41. V. Sahula and C. P. Ravikumar, Design planning for single chip implementation of wireless mobile transceiver, IEEE International Conference on Personal Wireless Communication, Hyderabad, Dec. 2000, Digital Object Identifier: 10.1109/ICPWC.2000.905765, 19-23.
42. V. Sahula and C. P. Ravikumar, Improving VLSI design processes using Hierarchical concurrent flow graph approach, 4th IEEE VLSI Design and Test Workshops, New Delhi, Aug. 2000.
43. V. Sahula and C. P. Ravikumar, Yield Oriented Design Planning for MCM based Systems, IMAPS International conference on Emerging Microelectronics and Interconnection Technology, Bangalore, Feb. 2000.
44. V. Sahula, C. P. Ravikumar and D. Nagchoudhuri, Optimal Interconnects: Modeling and Synthesis, IMAPS International conference on Emerging Microelectronics and Interconnection Technology, Bangalore, Feb. 1998.
45. "Mahanth Prasad, V. Sahula, and V. K. Khanna Zinc Oxide deposition and etching for MEMS acoustic sensor” IETE Diamond Jubilee National Seminar on Sensors-Technology & Applications, STA P14, Aug. 29-30, 2013
46. Alok Sharma and V. Sahula. Reconfiguration approaches for power aware prototyping: Case study of ATM cell assembler, National Conference on VLSI Design, CEERI Pilani, India, 12-14 Oct. 2011.
46. Lokesh Garg, Pramod Khandelwal, D. Boolchandani and V. Sahula. Improved sampling methodology for variability aware sizing of analog circuits, National Conference on VLSI Design, CEERI Pilani, India, 12-14 Oct. 2011.
47. D. Mathur, S. K. Bhatnagar and V. Sahula. LTCC: 3D Integration Multilayer Technology for Emerging Wireless Communication Micro-System Architectures, Indian Engineering Congress, NITk Surathkal, Sept. 2009.
48. D. Mathur, S. K. Bhatnagar and V. Sahula. Technologies for Microsystems beyond System-on-Chip, , IE National Seminar on Advanced Electronic Systems- Modeling & Simulation (Verification), Aug. 2008.
49. S. Samariya and V. Sahula. System Level Design & Verification: A Case Study of MPEG-2 Video Decoder, , IE National Seminar on Advanced Electronic Systems- Modeling & Simulation (Verification), Aug. 2008.
50. D. Boolchandani, Mohd. A. Ahmed and V. Sahula. Sizing of Analog Circuits using Support Vector Machine model, IE National Seminar on Advanced Electronic Systems- Modeling & Simulation (Verification), Aug. 2008.
51. A. Mundra and V. Sahula. “Using Model Checking for evaluation of arbitration schemes in IBM’s CoreConnect bus protocol”, Institute of Engineers (I) National Convention & Seminar on Advances in Electronics and Telecommunication: Vision 2020, Jaipur, 4-5 August 2006.
52. A. Singhal, Ulhas Deshmukh and V. Sahula. “USB Bus architecture for ARM Processor based System-on-Chip (SoC) Communication”, Institute of Engineers (I) National Convention & Seminar on Advances in Electronics and Telecommunication: Vision 2020, Jaipur, 4-5 August 2006.
53. Lintu Rajan and V. Sahula, Application of Concept Algebra in making inferences and role of Machine Learning, International Workshop on Computational Intelligence, TAFD, IIT Kanpur, July, 2013.
54. Ulhas Deshmukh and V. Sahula. “Stochastic Modeling approach for SoC Communication”, Symposium on Special functions & applications to Engineering Sciences, Jaipur, 16-17 Dec. 2007.
55. V. Sahula. “Challenges & Implications for VLSI Architectures for Multimedia Processing”, National Symposium on Mobile Handsets, Jaipur, April 2005.
56. Sahula, V. “VLSI CAD: Design Methodologies & algorithms”, IETE Annual Zonal seminar on “Electronic Design Automation: Issues & Challenges”, Jaipur, May 2003.
57. Boolchandani, D. and Sahula, V. “On modeling of Chip Interconnects”, IETE Annual Zonal seminar on “Electronic Design Automation: Issues & Challenges”, Jaipur, May 2003.
58. Bali, B. and Sahula, V., “BDDs applications into formal verification”, IETE Annual Zonal seminar on “Electronic Design Automation: Issues & Challenges”, Jaipur, May 2003.
59. Bhargava, M., Bhargava, L. and Sahula, V., “A study of low power design techniques for ASIPs, IETE Annual Zonal seminar on “Electronic Design Automation: Issues & Challenges”, Jaipur, May 2003.
60. Tiwari, R, and Sahula, V., “Output prediction based High performance CMOS logic: A comparative study”, IETE Annual Zonal seminar on “Electronic Design Automation: Issues & Challenges”, Jaipur, May 2003.
61. V. Sahula, Watermarking for intellectual property rights protection: An Overview, IETE Annual seminar on “E-Governance”, Jaipur, May 2002.
62. V. Sahula, C. P. Ravikumar and D. Nagchoudhuri. Design methodologies for Design of Wireless Mobile Transceivers: A tutorial”, IETE Annual seminar on Wireless Communications, Jaipur, May 2001.
63. V. Sahula and C. P. Ravikumar, Improving VLSI design processes using Hierarchical concurrent flow graph approach, 4th IEEE VLSI Design and Test Workshops, New Delhi, Aug. 2000.
64. V. Sahula and C. P. Ravikumar, Extended Signal Flow Graph Technique for Concurrent VLSI Design Processes, 3rd IEEE VLSI Design and Test Workshops, New Delhi, Aug. 1999.
65. V. Sahula, C. P. Ravikumar and D. Nagchoudhuri, VLSI Design Flow Management, 2nd IEEE VLSI Design and Test Workshops, New Delhi, Aug. 1998.
66. V. Sahula, Multi-valued Logic Function Minimization and Review of HW Implementation
Techniques, Indian Science Congress, Jaipur, Jan. 1995.