Princpal
coordinator, SMDP-VLSI Phase-2 project sponsored by Ministry of COmm.
& IT, Govt. of India, 2006-2012 (~60 Lakhs)
Principal Investigator, MHRD sponsored research project entitled“Synthesis
and Reduced Order Modeling of Interconnects for Deep Sub-micron Custom
Integrated Circuits and FPGAs” 2004-2007 (3.5 Years, ~ 8 Lakhs)
Co-investigator, MHRD modernization project entitled “Modernization
& Augmentation of facilities in Advance Electronics Lab for
Electronic Circuit Test and Data Acquisition”, 2004 (2 years, funds
merged with TEQIP funds for ECE dept., ~10 Lakhs)
Technical Reports
V. Sahula, C. P. Ravikumar. A Modeling and Improvement approach for Electronic Products’ Design Processes. Tech. Report, Deptt. of EE, IIT, Delhi, November 2000. (Submitted to Motorola, USA; This work was supported by Motorola, USA)
V. Sahula, Interconnect Centric CAD Tools for FPGA Physical Design, ECE MNIT Jaipur 2005-06.(submitted to ST-Microelectronics, New Delhi)
Part-I: An Evaluation of a-Priori Interconnect prediction Techniques, August 2005
Part-II: Multi-objective optimal routing for Island style FPGAs, August 2006
V. Sahula, An evaluation of USB Model: A case study of SoC
communication architecture for ARM processor based components, ECE MNIT
Jaipur, August 2006. (Submitted to CoWare, New Delhi)
V. Sahula, Interconnect Aware CAD Tools, ECE MNIT Jaipur, 2009. (submitted to MHRD, Govt. of India)